lttng_event_perf_counter_ctx Struct Reference

perf counter context field descriptor. More...

#include <event.h>

Data Fields
uint64_t	config
	perf counter configuration.
char	name [LTTNG_SYMBOL_NAME_LEN]
	Context field name.
uint32_t	type
	perf counter type ID.

Detailed Description

perf counter context field descriptor.

If the lttng_event_context::ctx member of an lttng_event_context structure is LTTNG_EVENT_CONTEXT_PERF_CPU_COUNTER or LTTNG_EVENT_CONTEXT_PERF_THREAD_COUNTER, then the lttng_event_context_u::perf_counter member of lttng_event_context::u selects a specific perf counter.

You must initialize such a structure to zeros before setting its members and using it, for example:

struct lttng_event_perf_counter_ctx perf_counter_ctx;
 
memset(&perf_counter_ctx, 0, sizeof(perf_counter_ctx));

Field Documentation

config

uint64_t lttng_event_perf_counter_ctx::config

perf counter configuration.

Depending on the lttng_event_perf_counter_ctx::type member:

0 (hardware counter)

One of:

Counter	ID
CPU cycles	0
Instructions	1
Cache references	2
Cache misses	3
Branch instructions	4
Branch misses	5
Bus cycles	6
Stalled cycles (front end)	7
Stalled cycles (back end)	8

1 (software counter)

One of:

Counter	ID
CPU clock	0
Task clock	1
Page faults	2
Context switches	3
CPU migrations	4
Minor page faults	5
Major page faults	6
Alignment faults	7
Emulation faults	8

3 (hardware cache counter)

The result of a bitwise OR operation between a cache ID, an operation ID, and a result ID, as follows:

Cache ID	Description
0	Data L1
1	Instructions L1
2	LL
3	Data TLB
4	Instruction TLB
5	Branch prediction unit (BPU)

Operator ID	Description
0	Read
0x100	Write
0x200	Prefetch

Result ID	Description
0	Access
0x10000	Miss

4 (PMU counter)

PMU counter raw ID.

See also

perf-record(1)

type

uint32_t lttng_event_perf_counter_ctx::type

perf counter type ID.

One of:

Type	ID
Hardware counter	0
Software counter	1
Hardware cache counter	3
Performance Monitoring Unit (PMU) counter	4